1. Field of the Invention
The present invention relates to a clock signal analysis device and a clock signal analysis method for analyzing delay values and clock skew values in clock signal transfer sections in a semiconductor integrated circuit while a layout pattern of the semiconductor integrated circuit is designed.
2. Description of the Related Art
Firstly, a RC extraction program is executed in order to extract circuit connection information from a layout pattern of the semiconductor integrated circuit during the analysis operation for delay values and skew values at clock signal transfer sections in the semiconductor integrated circuit. After this extraction process, a simulation must be executed by a circuit simulator.
However, because there are enormous number of parasitic resistances and parasitic capacitors in the extracted circuit connection information and a clock signal is provided to several thousands of circuit elements, it is impossible to detect and then edit signal termination nodes by hands.
Thus, because the analysis of the clock signal during the conventional design for the semiconductor integrated circuit is performed based on the above manner, it is almost impossible to detect signal termination nodes and to process the detected nodes by hands because there are enormous number of parasitic resistances and parasitic capacitors in the extracted circuit connection information.
Furthermore, the conventional analysis can not obtain supplemental information to trace a connection relationship of a clock buffer and to know a presence of a position having a large delay value and a large skew value in an actual layout pattern of the semiconductor integrated circuit in order to improve the delay values and the skew values in the clock signal transfer section based on the analysis result of the simulation. Because of this conventional drawback, the analysis result of the simulation can not be adequately used for improving the design of the semiconductor integrated circuit.
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a clock signal analysis device and a clock signal analysis method capable of efficiently executing the analysis of delay values and skew values in a layout pattern of a semiconductor integrated circuit, and providing supplemental information showing positions having a large delay value and a large skew value. Thereby, the clock signal analysis device and the clock signal analysis method according to the present invention are capable of reducing a design time of the semiconductor integrated circuit.
In accordance with a preferred embodiment of the present invention, a clock signal analysis device comprises first memory means for storing circuit connection information including transistor information and net information, the transistor information comprising logical gates such as clock buffers and the net information comprising parasitic resistances and parasitic capacities of wires among transistors to be used during analysis for delay/skew values in clock signal propagation paths in a semiconductor integrated circuit, second memory means for storing transistor characteristic information to be used during a simulation for circuit operation of the semiconductor integrated circuit, third memory means for storing control information to be used for controlling an execution of the analysis of delay/skew values, pre processing means for inputting the circuit connection information stored in the first memory means, the transistor characteristic information stored in the second memory means, the control information stored in the third memory means, and for editing the circuit connection information, the transistor characteristic information, and the control information, simulation execution means for inputting the edited information transferred from the pre processing means and for executing the simulation of circuit operation of the semiconductor integrated circuit by using a circuit simulator and a switch level simulator, and after processing means for inputting simulation results transferred from the simulation execution means, and for calculating a delay value of each clock signal terminal node from each clock signal input node, a skew value as a different between the delay values of the clock signal terminal nodes, a rising time of the clock signal, and a falling time of the clock signal, and for transferring the calculated delay values, the skew values, the rising time, and the falling time as simulation analysis results in order to display the simulation analysis results on display means. In the clock signal analysis device, the pre processing means edits the circuit connection information into an usable state for the simulation, and the after processing means displays the simulation analysis results executed by the simulation means on a two-dimensional distribution map through the display means.
In the clock signal analysis device as another preferred embodiment of the present invention, the pre processing means makes connection information comprising the circuit connection information other than the parasitic resistances and the parasitic capacities based on the circuit connection information including the transistor information comprising the logical gates such as clock buffers and the net information comprising the parasitic resistances and the parasitic capacities of the wires among the transistors stored in the first memory means, and decides all of clock signal terminal nodes by searching a clock signal propagation path from a starting net to which the clock signal is inputted to a following net in order through logical gates including inverters, clocked inverters, and optional logical gates.
In the clock signal analysis device as another preferred embodiment of the present invention, the pre processing means searches and decides un-necessary transistors connected to the starting net in the circuit connection information including the transistor information comprising the logical gates such as clock buffers and the net information comprising the parasitic resistances and the parasitic capacities of the wires among the transistors stored in the first memory means, and then eliminates the un-necessary transistors from the circuit connection information. In the clock signal analysis device, the pre processing section shorts all of nodes that do not connect other circuit elements in order to generate a clock signal input node.
In the clock signal analysis device as another preferred embodiment of the present invention, the pre processing means makes connection information comprising the circuit connection information other than the parasitic resistances and the parasitic capacities based on the circuit connection information including the transistor information comprising the logical gates such as clock buffers and the net information comprising the parasitic resistances and the parasitic capacities of the wires among the transistors stored in the first memory means, and displays a configuration of the logical gates in the clock signal propagation paths on the display means.
In the clock signal analysis device as another preferred embodiment of the present invention, the pre processing means decides that gate terminals of transistor connected to a designated net are clock signal intermediate nodes based on the circuit connection information including the transistor information comprising the logical gates such as clock buffers and the net information comprising the parasitic resistances and the parasitic capacities of the wires among the transistors stored in the first memory means, and the pre processing means then calculates a delay value from the clock signal input node to the clock signal terminal node, and a difference between the clock signal intermediate nodes.
In the clock signal analysis device as another preferred embodiment of the present invention, in the circuit connection information including the transistor information comprising the logical gates such as clock buffers and the net information comprising the parasitic resistances and the parasitic capacities of the wires among the transistors stored in the first memory means, the pre processing means replaces a transistor whose gate terminal is connected to the clock signal termination node with a capacitor located between the clock signal termination node and a ground.
In the clock signal analysis device as another preferred embodiment of the present invention, in the circuit connection information including the transistor information comprising the logical gates such as clock buffers and the net information comprising the parasitic resistances and the parasitic capacities of the wires among the transistors stored in the first memory means, the pre processing means connects a gate terminal of a transistor that is not connected to any optional node to a power source or a ground in order to eliminate a floating node.
In the clock signal analysis device as another preferred embodiment of the present invention, in the circuit connection information including the transistor information comprising the logical gates such as clock buffers and the net information comprising the parasitic resistances and the parasitic capacities of the wires among the transistors stored in the first memory means, the pre processing means connects a source terminal or a drain terminal of a transistor that is not connected to any optional node to a power source or a ground in order to eliminate a floating node.
In the clock signal analysis device as another preferred embodiment of the present invention, the pre processing means obtains a minimum coordinate and a maximum coordinate in coordinate information for all nodes involved in the circuit connection information, calculates virtual lattice points as virtual lattice coordinates by dividing a length between the minimum coordinate and the maximum coordinate into equal length, and decides nodes that are the nearest point to the virtual lattice points as observation points, and pre processing means classifies delay values and skew values from the clock signal input node to the observation nodes per optional length, and then makes a two-dimensional distribution map by coloring color codes per optional length, and displays the two-dimensional distribution map through the display means in order to reduce an amount of a used resource during a simulation for the nodes having the coordinates that are the nearest nodes to the virtual lattice points.
In the clock signal analysis device as another preferred embodiment of the present invention, the pre processing means displays the clock signal propagation paths of the wiring from the clock signal input node to the clock signal termination nodes by using all of coordination information through the display means.
The clock signal analysis device as another preferred embodiment of the present invention, further comprises a fourth memory. In the clock signal analysis device, the after processing means writes a minimum value, a maximum value, a mean value of each of calculated delay values, skew values, rising time, and falling time, and a statistic results of them into the fourth memory means.
In the clock signal analysis device as another preferred embodiment of the present invention further comprises layout pattern generation means. In the clock signal analysis device, the layout pattern generation means receives delay values and skew values that have been calculated in order to improve the delay values and the skew values in the clock signal propagation paths based on the minimum value, the maximum value, and the mean value of each of the delay values, the skew values, the rising time, and the falling time stored in the fourth memory means by the after processing means, and wherein the layout pattern generation means generates a layout pattern of the semiconductor integrated circuit based on the delay value and the skew value that have been back annotated.
In the clock signal analysis device as another preferred embodiment of the present invention, the pre processing means decides all of nodes involved in a designated net as observation nodes based on the circuit connection information including the transistor information comprising the logical gates such as clock buffers and the net information comprising the parasitic resistances and the parasitic capacities of the wires among the transistors stored in the first memory means. In the clock signal analysis device, the after processing means calculates a delay value per unit length for each of the parasitic resistances based on a difference of the delay values between both terminal nodes of the designated net and the coordinate values of the both terminal nodes, searches the connection information along clock signal propagation paths in the designated net involved in the circuit connection information, checks and extracts coordinates at which the delay value per unit length of the parasitic resistance is changed over an optional allowed value, and displays the extracted coordinates through the display means.
In accordance with another preferred embodiment of the present invention, a clock signal analysis method comprising the steps of a first memory step for storing circuit connection information including transistor information and net information, the transistor information comprising logical gates such as clock buffers and the net information comprising parasitic resistances and parasitic capacities of wires among transistors to be used during analysis for delay/skew values in clock signal propagation paths in a semiconductor integrated circuit, a second memory step for storing transistor characteristic information to be used during a simulation for circuit operation of the semiconductor integrated circuit, a third memory step for storing control information to be used for controlling an execution of the analysis of delay/skew values, a pre processing step for inputting the circuit connection information, the transistor characteristic information, the control information, and for editing the circuit connection information, the transistor characteristic information, and the control information, a simulation execution step for inputting the edited information obtained from the pre processing step and for executing the simulation of circuit operation of the semiconductor integrated circuit by using a circuit simulator and a switch level simulator, and an after processing step for inputting simulation results obtained from the simulation execution step, and for calculating a delay value of each clock signal terminal node from each clock signal input node, a skew value as a different between the delay values of the clock signal terminal nodes, a rising time of the clock signal, and a falling time of the clock signal, and for transferring the calculated delay values, the skew values, the rising time, and the falling time as simulation analysis results in order to display the simulation analysis results. In the clock signal analysis method, the pre processing step edits the circuit connection information into an usable state for the simulation, and the after processing step displays the simulation analysis results obtained by the simulation step on a two-dimensional distribution map through a display step.
The clock signal analysis method as another preferred embodiment of the present invention further comprises the steps of a fourth memory step for storing a minimum value, a maximum value, a mean value of each of the delay values, the skew values, the rising time and the falling time, and the statistic values of them, and a layout pattern generation step for generating a layout pattern of the semiconductor integrated circuit based on the information obtained from the fourth memory step in order to improve the delay values and the skew values of the clock signal propagation paths based on the delay values and the skew values that have been back annotated.